FIG. 1 shows a basic Class AB amplifier 10. A bipolar (i.e. split level) power supply outputs the voltages V+, V− and these output voltages are applied across the amplifier 10, which amplifies an input signal Sin and outputs a ground-referenced amplified output signal Sout to a load 20. Provided the voltages V+, V− supplied to the amplifier 10 are sufficient, the amplifier 10 has a substantially linear amplification (ignoring crossover effects). That is, the voltages V+, V− output from the power supply must be adequate so as to avoid output signal “clipping”, i.e. attenuation of the output when the signal nears, equals or exceeds the voltages V+, V− output from the power supply to the amplifier. This is avoided by having “headroom” between the maximum output signal Soutmax, and the power supply rails.
FIG. 2 is a graph showing Sout where Sin is a sine wave.
In this example, V+ and V− are set sufficiently high so that the input sine wave is linearly amplified. That is, there is a small amount of headroom between V+ and V− and the maximum output signal, so that the signal is not clipped.
The shaded region of the graph is representative of the power wasted in the amplifier 10; it can be seen that the amplifier 10 is very efficient when the output is close to V+ or V−, but very inefficient when the output is close to 0 V (GND). That is, a large amount of power is still being expended by the amplifier 10 even when the output signal Sout is small. The maximum theoretical efficiency for a class AB amplifier is 78.5%.
Class G amplifiers overcome this imitation on efficiency by providing more than one set of power supply rails, i.e. supply voltages. That is, as shown in FIG. 3, the amplifier may run off one power supply V+−V− if the output signal Sout is relatively large, or another smaller power supply Vp-Vn If the output signal Sout is relatively small. Ideally, an infinite number of power supply rails would be provided, such that the voltage supplied to the amplifier effectively “tracks” the input signal, always providing just enough voltage so that there is no clipping.
FIG. 4 shows an example of a Class G amplifier 50.
In this example the signal source is digital in nature so a digital signal Sin to be amplified is input to the amplifier 50. The digital input signal is first converted to an analogue signal by a digital-to-analogue converter (DAC) 51. The resulting analogue signal is fed to an envelope detector 52. The envelope detector 52 detects the size of the envelope of the analogue output signal of the DAC 51, and outputs a control signal to a switching DC-DC converter 54. The control signal is indicative of the magnitude of the envelope of the analogue output of the DAC 51. The DC-DC converter 54 then supplies voltages V+ and V− to a power amplifier 56 by charging respective capacitors 58, 60. The voltages V+ and V− supplied by the DC-DC converter 54 vary with the control signal from the envelope detector 52, such that a relatively large envelope will lead to relatively high voltages supplied to the power amplifier 56; conversely, a small envelope will lead to relatively small voltages being supplied to the power amplifier 56, so that less power is wasted.
V+ is supplied to one terminal of a first capacitor 58, and V− is supplied to one terminal of a second capacitor 60. The second terminals of the respective capacitors 58, 60 are connected to ground. The DC-DC converter 54 is switched on and off at a fixed frequency Fs, so that the capacitors 58, 60 are alternately charged and discharged, with an approximately constant voltage being applied to the power amplifier 56 provided the envelope of the analogue signal does not change.
FIG. 5 is a schematic graph illustrating the voltage across one of the capacitors 58, 60. At time t0, the DC-DC converter 54 is switched on and the capacitor begins to charge. At time t1, the DC-DC converter 54 is switched off and the capacitor begins to discharge. At time t2, the DC-DC converter 64 is switched on and the capacitor begins to charge again. This action repeats, such that the voltage across the capacitor is maintained at an approximately constant level, with a small amount of variation known as the “ripple voltage”. The time period between t0 and t2 is 1/Fs.
In parallel with the envelope detection discussed above, the analogue output signal of the DAC 51 in FIG. 4 is fed through an analogue delay 62 to a preamplifier 63, typically a programmable gain amplifier (PGA), which amplifies the delayed signal by a gain set in accordance with a received control signal (i.e. the volume). The output from the preamplifier 63 is fed to the power amplifier 56, where it is amplified and output to a load 64. The analogue delay 62 is necessary so that the power modulation achieved by the envelope detection is synchronized with the signal arriving at the power amplifier 56.
However, analogue delays often cause distortion of the signal; the longer the delay that is required, the worse the distortion of the delayed signal. Conventionally, to minimize this effect, the envelope detection and power modulation must be made to operate as quickly as possible; that is, the DC-DC converter 54 must react quickly to changes in the input signal envelope. However, this approach also has drawbacks. For example, where the power amplifier 56 is used to amplify an audio signal, a DC-DC converter that operates at the frequencies necessary to reduce distortion in the signal may itself generate noise tones that are audible to a user. In practice, a compromise needs to be reached between distortion of the signal and noise generated by the power supply.
As described above in FIG. 5, the voltage across the capacitors 58, 60 rises and falls periodically as the DC-DC converter 54 is switched on and off at a certain clock frequency, giving rise to a “ripple voltage”. A problem with such systems is that the ripple voltage tends to generate “tones” at the clock frequency and its harmonics. The greater the ripple voltage, the greater the amplitude of the tones created. In general, such tones are undesirable and may disturb the operation of other systems on the chip. In audio applications, such tones may mix into audio frequencies, and be audible to the user.
A standard method of reducing the tones caused by switching in the power supply is to dither the switching frequency. That is, by adding a noise signal to the clock signal, the switching frequency may be continuously adjusted slightly up or down. This has the effect of “spreading out” the energy generated at the clock frequency and its harmonics to cover a broader range of frequencies around those discrete values. This lessens the amplitude of the tones, reducing their impact on other systems and the end user.
However, power is required to generate dither. This is particularly a disadvantage in portable applications, where battery life is an important consideration for manufacturers. In addition, the dither added to the switching frequency may actually cause unwanted noise in the other systems on the chip, i.e. because the DC-DC converter 54 is not switching at the “optimum” frequency.